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Sign extension is the operation, in computer arithmetic, of increasing the number of bits of a binary number while preserving the number's sign (positive/negative) and value. This is done by appending digits to the most significant side of the number, following a procedure dependent on the particular signed number representation used. For example, if six bits are used to represent the number " 00 1010" (decimal positive 10) and the sign extend operation increases the word length to 16 bits, then the new representation is simply "0000 0000 0000 1010". Thus, both the value and the fact that the value was positive are maintained.If ten bits are used to represent the value " 11 1111 0001" (decimal negative 15) using two's complement, and this is sign extended to 16 bits, the new representation is "1111 1111 1111 0001". Thus, by padding the left side with ones, the negative sign and the value of the original number are maintained.In the Intel x86 instruction set, for example, there are two ways of doing sign extension: * using the instructions cbw, cwd, cwde, and cdq: convert byte to word, word to doubleword, word to extended doubleword, and doubleword to quadword, respectively (in the x86 context a byte has 8 bits, a word 16 bits, a doubleword and extended doubleword 32 bits, and a quadword 64 bits); * using one of the sign extended moves, accomplished by the movsx ("move with sign extension") family of instructions. ==References== * Mano, Morris M.; Kime, Charles R. (2004). ''Logic and Computer Design Fundamentals'' (3rd ed.), pp 453. Pearson Prentice Hall. ISBN 0-13-140539-X. de:Zweierkomplement#Vorzeichenerweiterung 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Sign extension」の詳細全文を読む スポンサード リンク
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